View CY25403FSXC_4170963.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
CY25403 CY25423
Three PLL Programmable Clock Generator with Spread Spectrum
Features
* Three fully integrated phase-locked loops (PLLs) * Input Frequency range: -- External crystal: 8 to 48 MHz -- External reference: 8 to 166 MHz clock * Wide operating output frequency range -- 3 to 166 MHz * Programmable Spread Spectrum modulation frequency range of 30 to 120 kHz with Lexmark profile * Center Spread: 0.125% to 2.5% * Down Spread: -0.25% to -5% * Frequency select feature with option to select four different frequencies * Low-jitter, high-accuracy outputs * Up to three clock outputs * Programmable output drive strength * Glitch-free outputs while frequency switching * Four independent output voltages: 3.3V, 3.0V, 2.5V, and 1.8V * 8-pin SOIC package * Commercial and Industrial temperature range
Benefits
* Multiple high-performance PLLs allow synthesis of unrelated frequencies * Nonvolatile programming for customized PLL frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies * Two Spread Spectrum capable PLLs with Lexmark profile for maximum for EMI reduction * Spread Spectrum PLLs can be disabled or enabled separately * PLLs can be programmed for system frequency margin tests * Meets critical timing requirements in complex system designs * Suitable for PC, consumer, and networking applications * Ability to synthesize standard frequencies with ease * Application compatibility in standard and low-power systems
Block Diagram
3 of 4 Crossbar Switch OSC PLL1 Output Dividers and Drive Strength Control CLK1 CLK2 CLK3
XIN XOUT
FS0 FS1 SSON
MUX and Control Logic
PLL2 (SS)
PLL3 (SS)
PD#/OE
Cypress Semiconductor Corporation Document #: 001-12564 Rev. *A
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 02, 2007
[+] Feedback
PRELIMINARY
CY25403 CY25423
Pin Configuration
XIN VDD CLK1 CLK2/FS0
1 2 3 4
8 LD SOIC
8 7 6 5
XOUT GND CLK3/SSON PD#/OE/FS1
Pin Description - Memory Programmable 3-PLL device with 2 Spread Spectrum PLLs
Pin Number 1 2 3 4 5 6 7 8 XIN VDD CLK1 CLK2/FS0 PD#/OE/FS1 CLK3/SSON GND XOUT Name Input Power Output Output/input Input Output/Input Power Output I/O Crystal or Clock Input Power Supply Programmable Clock Output Programmable Clock Output or FS0 Power Down, Output Enable or FS1 Programmable Clock Output or SSON Power Supply Ground Crystal Output for center spread is from 0.125% to 2.50%. The range for down spread is from -0.25% to -5.0%. Contact the factory for smaller or larger spread percentage amounts, if required. The input to the CY25403 and CY25423 is either a crystal or a clock signal. The input frequency range for crystals is 8 MHz to 48 MHz, and for clock signals is 8 MHz to 166 MHz. The CY25403 and CY25423 have up to three clock outputs and each output has four possible input sources.There are two frequency select lines FS(1:0) that provide an option to select four different sets of frequencies among the each of the three PLLs. Each output has programmable output divider options. Output 1 has eight possible divider values and outputs 2-3 have four possible divider values for maximum flexibility. The 2 bit or 3 bit output dividers are programmable providing a wide output frequency range. The outputs are glitch-free when frequency is switched using output dividers. The outputs have a predictable phase relationship, if the clock source is the same PLL and divider values are 2, 3, 4, or 6. The CY25403 and CY25423 are 3-PLL memory programmable spread spectrum clock generators with three clock outputs. Table 1. Supply Voltage Options Device CY25403 CY25423 VDD Supply Voltage 2.5V, 3.0V or 3.3V 1.8V Description
General Description
Th CY25403 and CY25423 are three PLL programmable Spread Spectrum Clock Generators used to reduce EMI found in high-speed digital electronic systems. Two of the three PLLs have Spread Spectrum capability. The spread spectrum feature are turned on or off using the control pin SSON. The advantage of having three PLLs is that a single device can generate up to three independent frequencies from a single crystal or reference input frequency. Generally, a design requires up to three oscillators to achieve the same result with a single CY25403 or CY25423. The device uses Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the input clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies are greatly reduced. This reduction in radiated energy significantly reduces the cost of complying with regulatory agency (EMC) requirements and improves time-to-market without degrading the system performance. The CY25403 and CY25423 use a factory/field-programmable configuration memory array to provide customization for output frequencies, frequency select options, spread characteristics like spread percentage and modulation frequency, output drive strength and crystal load capacitance. A customized device can be configured using CyberclocksTM software or by contacting the factory. The spread percentage is programmed to either center spread or down spread with various spread percentages. The range
Document #: 001-12564 Rev. *A
Page 2 of 8
[+] Feedback
PRELIMINARY
CY25403 CY25423
Absolute Maximum Conditions
Parameter
VDD VIN TS ESDHBM UL-94 MSL
Description
Supply Voltage Input Voltage Temperature, Storage ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Relative to VSS Non Functional
Condition
Min.
-0.5 -0.5 -65 2000 V-0
Max.
4.5 +150
Unit
V C Volts
VDD + 0.5 VDC
MIL-STD-883, Method 3015 @1/8 in. SOIC package
-
1
Recommended Operating Conditions
Parameter
VDD1 VDD2 VDD3 VDD4 TAC TAI CLOAD tPU Operating Voltage, 3.3V Operating Voltage, 3.0V Operating Voltage, 2.5V Operating Voltage, 1.8V Commercial Ambient Temperature Industrial Ambient Temperature Max. Load Capacitance Power-up time for all VDD pins to reach minimum specified voltage (power ramps must be monotonic)
Description
Min.
3.0 2.7 2.25 1.65 0 -40 - 0.05
Typ.
- - - - - - - -
Max. Unit
3.6 3.3 2.75 1.95 +70 +85 15 500 V V V V C C pF ms
DC Electrical Specifications
Parameter
VOL VOH VIL VIH VILX VIHX
Description Output Low Voltage, All CLK pins Output High Voltage, All CLK pins All Inputs except XIN All Inputs except XIN Input Low Voltage, clock input to XIN pin Input High Voltage, clock input to XIN pin
Conditions All VDD levels, IOL = 8 mA All VDD levels, IOH = -8 mA All VDD levels All VDD levels All VDD levels All VDD levels
Min. 0 VDD - 0.4 -0.3 0.8 * VDD -0.3 1.44 - - - - - -
Typ. - - - - - - - - - - - -
Max. 0.4 VDD 0.2 * VDD VDD + 0.3 0.36 2.0 10 1 1 10 17 7
Unit V V V V V V A A A A mA pF
IILPDOE IIHPDOE IILSR IIHSR
IDD[1] CIN
Input Low Current, PD#/OE and FS0,1 pins VIN = VSS (Internal pull up = 100k typical) Input High Current, PD#/OE and FS0,1 pins VIN = VDD (Internal pull up = 100k typical) Input Low Current, SSON pin Input High Current, SSON pin
Supply Current Input Capacitance - All inputs except XIN
VIN = VSS (Internal pull down = 100k typical) VIN = VDD (Internal pull down = 100k typical)
All clocks running, CL = 0 SSON, OE, PD# or FS inputs
Note 1. Configuration dependent.
Document #: 001-12564 Rev. *A
Page 3 of 8
[+] Feedback
PRELIMINARY
CY25403 CY25423
AC Electrical Specifications
Parameter
FIN (crystal) FIN (clock) FOUT DC DC
Description
Crystal Frequency Input Clock Frequency (XIN) Output Clock Frequency
Conditions
Min.
8 8 3 45
Typ. Max. Unit - - -
50 48 166 166 55 MHz MHz MHz %
Output Duty Cycle All Clocks except Ref Out Duty Cycle is defined in Figure 2; t1/t2, 50% of VDD Ref Out Duty Cycle Ref In Min 45%, Max 55%
40 0.8 0.8 - - - - - -
60 - - - - 3
% V/ns V/ns ps ns ms
ER EF TCCJ1 TLTJ T10
CLK1-3 Rising Edge Rate CLK1-3 Falling Edge Rate Cycle-to-cycle Jitter Long Term Jitter PLL Lock Time
VDD = All, 20% to 80% VDD VDD = All, 20% to 80% VDD Configuration dependent. See Table 2 Configuration dependent. See Table 2
Table 2. Configuration Example for Jitter Reference 27MHz 27MHz 48 MHz 48 MHz Description TCCJ1 TLTJ TCCJ1 TLTJ Max Jitter (ps) on Output 1(48MHz) 155 770 135 535 Max Jitter (ps) on Output 2 (27 MHz) 255 580 225 575 Max Jitter (ps) on Output 3 (166 MHz) 170 630 100 520
Recommended Crystal Specification for SMD Package
Parameter Fmin Fmax R1(max) C0(max) CL(max) DL(max) Minimum Frequency Maximum Frequency Maximum Motional Resistance (ESR) Maximum Shunt Capacitance Maximum Parallel Load Capacitance Maximum Crystal Drive Level Description Range 1 Range 2 Range 3 8 14 135 4 18 300 14 28 50 4 14 300 28 48 30 2 12 300 Unit MHz MHz pF pF W
Recommended Crystal Specification for Thru-Hole Package
Parameter Fmin Fmax R1(max) C0(max) CL(max) DL(max) Minimum Frequency Maximum Frequency Maximum Motional Resistance (ESR) MaximumShunt Capacitance Maximum Parallel Load Capacitance Maximum Crystal Drive Level Description Range 1 Range 2 Range 3 8 14 90 7 18 1000 14 24 50 7 12 1000 24 32 30 7 12 1000 Unit MHz MHz pF pF W
Document #: 001-12564 Rev. *A
Page 4 of 8
[+] Feedback
PRELIMINARY
CY25403 CY25423
Test and Measurement Setup
Figure 1. Test and Measurement Setup
V DDs 0.1 F DUT Outputs C LOAD
GND
Voltage and Timing Definitions
Figure 2. Duty Cycle Definition
t1 t2 VDD 50% of VDD Clock Output 0V
Figure 3. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4
t3 t4 V DD 80% of VDD 20% of VDD 0V
Clock Output
Document #: 001-12564 Rev. *A
Page 5 of 8
[+] Feedback
PRELIMINARY
CY25403 CY25423
Ordering Information
Part Number[2] Lead-free CY25403SXC-xxx CY25403SXC-xxxT CY25403FSXC CY25403FSXCT CY25423SXC-xxx CY25423SXC-xxxT CY25423FSXC CY25423FSXCT CY25403SXI-xxx CY25403SXI-xxxT CY25403FSXI CY25403FSXIT CY25423SXI-xxx CY25423SXI-xxxT CY25423FSXI CY25423FSXIT 8-pin SOIC 8-pin SOIC-Tape & Reel 8-pin SOIC 8-pin SOIC-Tape & Reel 8-pin SOIC 8-pin SOIC-Tape & Reel 8-pin SOIC 8-pin SOIC-Tape & Reel 8-pin SOIC 8-pin SOIC-Tape & Reel 8-pin SOIC 8-pin SOIC-Tape & Reel 8-pin SOIC 8-pin SOIC-Tape & Reel 8-pin SOIC 8-pin SOIC-Tape & Reel 3.3, 3.0 or 2.5 3.3, 3.0 or 2.5 3.3, 3.0 or 2.5 3.3, 3.0 or 2.5 1.8 1.8 1.8 1.8 3.3, 3.0 or 2.5 3.3, 3.0 or 2.5 3.3, 3.0 or 2.5 3.3, 3.0 or 2.5 1.8 1.8 1.8 1.8 Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Industrial, -40C to +85C Industrial, -40C to +85C Industrial, -40C to +85C Industrial, -40C to +85C Industrial, -40C to +85C Industrial, -40C to +85C Industrial, -40C to +85C Industrial, -40C to +85C Type VDD(V) Temperature Range
Note 2. xxx Indicates Factory Programmable are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative. F in the part number indicates field programmable using CyberClocks Online software.
Document #: 001-12564 Rev. *A
Page 6 of 8
[+] Feedback
PRELIMINARY
Package Drawing and Dimensions
Figure 4. 8-lead (150-Mil) SOIC S8
PIN 1 ID
CY25403 CY25423
4
1
1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012
0.230[5.842] 0.244[6.197]
0.150[3.810] 0.157[3.987]
4. PACKAGE WEIGHT 0.07gms
PART # S08.15 STANDARD PKG. 5 8 SZ08.15 LEAD FREE PKG.
0.189[4.800] 0.196[4.978]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249]
51-85066-*C
0.0138[0.350] 0.0192[0.487]
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-12564 Rev. *A
Page 7 of 8
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
PRELIMINARY
CY25403 CY25423
Document History Page
Document Title: CY25403/CY25423 Three PLL Programmable Clock Generator with Spread Spectrum Document Number: 001-12564 REV. ** *A ECN NO. 690339 815816 Issue Date See ECN See ECN Orig. of Change RGL RGL New Data Sheet Minor Change: To Post on web Description of Change
Document #: 001-12564 Rev. *A
Page 8 of 8
[+] Feedback

▲Up To Search▲

Price & Availability of CY25403FSXC

	To Download CY25403FSXC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .